The Uncertain Future of Moore’s Law
The Rise of 3-D Transistors and What it Means for Technology in the 21st Century
For examples of how digital technology is rapidly, profoundly, and unexpectedly shaping lives across the globe, look no further than today’s news: social media and the Arab Spring; the Stuxnet worm and the clandestine cyberwar against Iran; the proliferation of smartphones and tablets; the ubiquitous web and the cloud; Netflix streaming surpassing web surfing on the net; Bradley Manning’s data dump to Wikileaks; and Microsoft as the new tech underdog. The digital world is changing rapidly, and so are we.
We have become accustomed to this state of perpetual flux, of this open-endedness in the application and proliferation of new digital technologies. Yet underneath this flux and unpredictability lies a shared certainty: The cost of digital electronics, and the technologies built with them, will dramatically plummet as their power and performance continues to rise exponentially.
This conviction about the future of digital electronics—silicon microchips—is widely known as “Moore’s Law,” named after Gordon Moore (a chemist and co-founder of both Fairchild Semiconductor and the Intel Corporation) for his explication of this developmental dynamic in silicon microchips in 1964.
We have already entered into an age of uncertainty about Moore’s Law itself.
Equal parts economic and technical, this developmental dynamic has been maintained for a half century by the semiconductor industry, through the efforts of thousands of researchers and the investment of hundreds of billions of dollars. Maintaining Moore’s Law has required a coordinated push in a single, common direction: shrinking the size of the basic building blocks of microchips—tiny switches known as planar transistors—and, to use Moore’s term, cramming more and more of them into the same area of a silicon chip. To semiconductor initiates, this common direction is known as CMOS scaling (CMOS is an acronym for the variety of microchip that rose to prominence in the 1970s and 1980s). In fact, since the 1990s the semiconductor industry along with its specialty manufacturing tool and materials partners have collaborated on the International Technology Roadmap for Semiconductors, a careful timeline of the problems that must be solved to maintain the traditional pace of change in silicon microchips.
The metronomic pace of CMOS scaling, largely taken for granted outside of certain technical communities, underlies our expectation of continual surprise in the digital world, from the continued proliferation of ever-more-powerful microchips. Our conviction in the reliability of Moore’s Law profoundly shapes the expectations and decisions of both producers and consumers of electronics-reliant goods and services. From military weapons systems to consumer electronics, product planning is grounded in Moore’s Law. As individual consumers, our purchasing decisions share this grounding: Who has not waited a year to buy a gadget, with the expectation that next year’s gadget version 2.0 will deliver much more bang for the buck?
But what we’ve taken for granted for decades may soon change. On Wednesday, May 4, some of the leading technologists at the Intel Corporation held a press conference to disclose details about their new silicon manufacturing technology. While there was much of interest in the Intel disclosures about the future of silicon microchips and the competitive landscape of the global semiconductor industry, perhaps the most important implication of the presentation has received little comment: We have already entered into an age of uncertainty about Moore’s Law itself. This conclusion is somewhat ironic, since Intel announced that it had succeeded in developing a new innovation that will extend Moore’s Law for at least another six years.
What did Intel disclose last month? In essence, Intel announced that it had abandoned the planar transistor, and, therefore, traditional CMOS scaling. As Mark Bohr, one of Intel’s most senior technologists put it in the press conference Q&A, “We can say goodbye to planar transistors.”
For the remarkable run of CMOS scaling over the past four decades, a defining feature of planar transistors was that they were flat; hence, their name. As planar transistors were shrunk so that a billion of them could be crammed into a single microchip, one problem became more and more pronounced. They became harder to turn off, a very bad thing for a switch. Solutions to this problem entailed a growing difficulty of their own: The improved transistors were power hungry, anathema to applications like smartphones, laptops, and tablets.
To continue shrinking transistors in order to maintain the pace of performance and cost improvement for microchips, and to untangle itself from this power dilemma, Intel announced a new manufacturing technology that it will begin to use for all of its products next year. In this technology, Intel will replace planar transistors with “Tri-Gate” transistors. These new transistors are no longer flat, but rather take the form of a minute rail or “fin.” Indeed, the more generic term of this new form of transistor, used by other semiconductor firms, is “finFET.” One of the principle virtues of these new non-flat or “3-D transistors” is that they are easy to turn off, and thus combine great switching speed with very low power consumption.
At left is a traditional 32-nanometer 2-D transistor, while at right is the newer, smaller, 22-nanometer 3-D transistor.
Intel is making the jump to its Tri-Gate transistors several years ahead of its semiconductor industry rivals, and sees them as providing a basis for its subsequent generation of manufacturing technology in the next six years. This new path to maintaining Moore’s Law, as the Intel researchers noted, builds on previous deviations in the last five years or more from traditional materials and structures for CMOS scaling. As Bill Holt, the Intel VP for technology development put it, “Simple CMOS scaling…ended a while ago.” In the midst of their press conference, the Intel team presented a quote about the move to 3-D transistors from none other than Gordon Moore himself: “For years we have seen limits to how small transistors can get. This change in the basic structure is a truly revolutionary approach, and one that should allow Moore’s Law, and the historic pace of innovation to continue.”
While Intel’s jump to the world beyond traditional CMOS provides a view into the immediate future of the world’s largest chipmaker, a considerable haze of uncertainty now surrounds what its rivals will do in the near term, and what the whole industry will do after six short years. For the immanent “22 nanometer” or “22 nm” technology for which Intel will use 3-D transistors—and which Intel claims will have the capability of cramming as many as 6 million such transistors into the area occupied by a standard printed period—many of its major competitors will maintain the planar transistor, and pursue an alternate approach to the power problem known as “silicon on insulator.” At the upcoming “14 nm” technology some three years down the line, the semiconductor industry could bifurcate, with larger firms abandoning planar for 3-D transistors—moving beyond CMOS—while smaller firms pursue the “silicon on insulator” technology.
This handy (and not-at-all corny) video Intel put together illustrates the difference between 2-D and 3-D transistor technology:
Looking out further toward 2016, at the “10 nm” technology for which development is already underway, the haze thickens. The optical technology used to form today’s microchips becomes increasingly improbable at that level of the nanoscale, and the top contenders to replace it are already late in their development to keep pace with Moore’s Law. Looking out less than a decade from now to the “7 nm” technology that is planned to follow 10 nm, the inherent atomic nature of matter looms as an issue for fabricating uniform devices. The diameter of a silicon atom is 0.2 nm.
As the semiconductor industry drives deeper into the nanoscale, it appears that we are returning to an age of technological uncertainty not dissimilar from the one from which silicon microchips first emerged. <pullquote>Such a return to a period in which the future of electronics was highly uncertain, and developments were far more unpredictable, could be both highly disruptive and incredibly exciting. <pullquote>
Disruption could occur in many forms. Patterns of technological change may become less uniform, with the magnitude of changes and their timescale disaggregating across different technologies. The management and funding of research and innovation may have to undergo considerable revision to adapt to uncertainty. On the one hand this means technological and economic planning may become significantly more difficult. On the other, creative and unexpected new directions in research might abound.
For most of the past 40 years, industry has conducted and financed the bulk of the R&D for CMOS scaling. In an age of increased technological uncertainty, government support of high-risk research may return to prominence. Indeed, direct military funding of R&D and activist, price-insensitive military demand were essential to the initial development of the microchip in the late 1950s and early 1960s. In this era, government research spending on microelectronics was significant, risk-tolerant, and open-ended, supporting a broad array of speculative approaches. It is interesting to note that the semiconductor community looks to DARPA-funded research at the University of California, Berkeley in the late 1990s as the origin of the 3-D transistor approach.
One conclusion to be drawn from Intel’s recent announcement is that while the immediate future of Moore’s Law appears clear, the longer term developmental path for electronics is now as, or more, uncertain than it has been for a half century. Previous news of the death of Moore’s Law has turned out to be exaggerated. The rather incredible extensibility of silicon technology and the creative potentials of the semiconductor community have repeatedly surmounted previous purported barriers. Surely silicon technology and microchips will continue to surprise even the most knowledgeable observers in the years ahead.
Nevertheless, with Intel’s leap to the world beyond traditional CMOS scaling and the planar transistor we appear to be quickly approaching a regime of increased technological uncertainty. Perhaps this is a return to a more typical state of affairs from a temporary excursion into unprecedented continuous and predictable change. “Doubt is not an agreeable condition,” Voltaire once quipped, “but certainty is an absurd one.”
David C. Brock is an historian of technology and the co-author of Makers of the Microchip (MIT Press, 2010). Brock is a Senior Research Fellow with the Center for Contemporary History and Policy at the Chemical Heritage Foundation, and is also affiliated with the Center for Nanotechnology in Society at the University of California, Santa Barbara.
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